Throughout the evolution of integrated circuits, the aim of device scaling has been to increase circuit performance and to increase the functional complexity of the circuits. At the outset, scaling down of active device sizes was a very effective means of achieving these goals. Eventually, however, the scaling of active devices became less profitable, as the limitations of the circuit speed and maximum functional density depends more on the characteristics of the interconnects than on the scaled devices. In addition, the aspects of silicon utilization, chip cost, and ease and flexibility of integrated circuit design have also been adversely affected by the interconnect technology restrictions. The solution to lifting these limitations have predominantly involved the implementation of multilevel-interconnect schemes.
In the course of integrated circuit evolution, the maximum number of devices per chip has steadily increased, mainly as a result of the increase in functional density. Typically, functional density is defined as the number of interconnected devices per chip area, while the number of devices per chip area is referred to as the active device density. As the minimum feature size on integrated circuits has decreased, the active device density has also increased. Eventually, the condition has been reached in which the minimum chip area has become interconnect limited--that is, the area needed to route the interconnect lines between the active devices has exceeded the area occupied by the active devices. Thus continued shrinking of active devices has produced less circuit performance benefits. To overcome this problem, multilevel-interconnection within the integrated circuits has been implemented, and as additional levels are added to multilevel-interconnection schemes and circuit features are scaled to submicron dimensions, the required degree of planarization is increased.
The term planarization is generally well known to those skilled in the art. Those skilled in the art are also familiar with the fact that there are varying degrees of planarization. For a more thorough discussion of this topic, see S. Wolf's, Silicon Processing for the VLSI Era, Vol. 2, which is incorporated herein by reference. A planarized surface, as used herein, shall mean a substantially planar surface--that is, it is a surface that typically is greater than ninety percent (90%) planar, rather than absolutely planar. Such planarization may be implemented in either the conductor or the dielectric layers. As the number of levels in an interconnect technology is increased, the stacking of additional layers on top of one another produces a more and more rugged topography. Therefore, it is apparent that the surface of the wafer must be planarized to lessen this roughness in subsequent levels. Without such planarization, the microscopic recessed areas that result on the wafer surface from the stacking of device features can lead to topography conditions that would eventually reduce the yield of circuits to unacceptably small values.
To over come these problems, various planarization techniques are now used to achieve a high degree of global planarization. One such technique is chemical mechanical polishing (CMP), which consists of a combination of applying chemicals to the dielectric layer followed by mechanically scrubbing the wafer. This expensive process removes a portion of the overlying dielectric across the wafer and results in a relatively global planarization.
Many problems arise, however, when a CMP process is employed during wafer planarization. Significant deviation from global planarity results due to pattern density effects. Where there is a high density of interconnect structures, CMP will not deliver a substantially uniform surface as the dielectric still exhibits effects of the underlying topology. To counter these topological effects, a thick layer of dielectric must be employed as the CMP process consequently removes a sizable portion of much of the coating. Subsequently, the overlying layer's thickness will vary with the underlying metal pattern density.
Additionally, use of CMP processes result in severe variations in dielectric across the wafer. Since there are significant buildups of the overlying layer in areas with a high density of metal interconnect structures, other areas of the wafer may experience disproportionate dielectric deposition. A thick dielectric layer combined with a large amount of the layer's removal required for conventional CMP commonly results in a significant wafer-wide lack of planarity.
Employing a CMP process in planarization also results in significant wafer to wafer and lot to lot variability on the remaining oxide due to systematic changes in CMP polish rate with number of wafers polished. The CMP process must be closely monitored throughout the production and customized each time a different device is produced. This results in high production costs and lost time as the fabrication equipment must be re-calibrated with each successive lot of wafers.
Accordingly, what is needed in the art is a method for planarizing an irregular surface of a semiconductor wafer that avoids the problems associated with prior art methods.